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Document Revision History
SV51008
2014.01.10
Document Revision History
Date
January 2014
May 2013
Version
2014.01.10
2013.05.06
Changes
? Updated the figure that shows the delay chains in the Stratix V I/O
block.
? Added related information link to ALTDQ_DQS2 Megafunction User
Guide for more information about using the delay chains.
? Added link to Altera's External Memory Spec Estimator tool to the
topic listing the external memory interface performance.
? Moved all links to the Related Information section of respective topics
for easy reference.
? Added link to the known document issues in the Knowledge Base.
? Added related information link to DDR2 and DDR3 SDRAM Board
Design Guidelines .
? Performed some minor text edits to improve accuracy.
December 2012
2012.11.28
?
?
?
?
Reorganized content and updated template.
Added RLDRAM 3 support.
Added performance information for external memory interfaces.
Separated the DQ/DQS groups tables into separate topics for each device
variant for easy reference.
?
?
?
?
?
Moved the PHYCLK networks pin placement guideline to the Planning
Pin and FPGA Resources chapter of the External Memory Interface
Handbook .
Removed guidelines on DDR2 and DDR3 SDRAM DIMM interfaces.
Refer to the relevant sections in the External Memory Interface
Handbook for the information.
Corrected “ Gray-code ” to “ Binary-Code ” in the “ Phase Offset Control ”
section.
Removed the topic about phase offset control.
Removed the topics about I/O and DQS configuration block bit
sequence. Refer to the relevant sections in the ALTDQ_DQS2
Megafunction User Guide .
June 2012
November 2011
1.4
1.3
?
?
?
?
?
Added Table 7 – 6, Table 7 – 8, and Table 7 – 9.
Updated Table 7 – 2, Table 7 – 3, and Table 7 – 7.
Updated Figure 7 – 18.
Updated the “ PHY Clock (PHYCLK) Networks ” section.
Added “ PHY Clock (PHYCLK) Networks ” section.
Altera Corporation
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?
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?
Updated “ Delay-Locked Loop ” section.
Updated Figure 7 – 3, Figure 7 – 5, and Figure 7 – 7.
Updated Table 7 – 2, Table 7 – 3, Table 7 – 4, Table 7 – 5, and Table 7 – 6.
Minor text edits.
External Memory Interfaces in Stratix V Devices
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